The present invention relates to the testing of integrated circuits. More specifically, in one embodiment, the invention provides an improved system for testing an integrated circuit. With the high level of complexity of integrated circuits, it is becoming increasingly difficult to test the integrated circuits to ensure that they were manufactured with no defects. Typically, a device under test (DUT) is tested by applying pre-determined waveform patterns to the DUT's input pins. A tester generates the waveforms and monitors the DUT's output pins to ensure that the device operates as expected.
Often, the waveform patterns needed to adequately test the DUT are complex. In turn, capturing the output from these complex waveform patterns requires relatively large amounts of memory and the memory requirements are becoming greater as the integrated circuits are becoming more complex. While running the test on a complex integrated circuit, variants of pieces of data go through the chip. Typically all the output data is dumped and collected as bit streams of ones and zeros. As this output is becoming larger, the time to analyze the data from the test and make any corrections to the integrated circuit is becoming greater. Consequently, the lead-time from first silicon to the ability to sell or distribute the integrated circuit is becoming greater.
As a result, there is a need to solve the problems of the prior art to reduce the amount of time required to debug and test a semiconductor device.